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femtoclocks? crystal-to-lvds frequency synthesizer ics844004-104 idt? / ics? lvds frequency synthesizer 1 ics844004AK-104 rev. a september 15, 2008 general description the ics844004-104 is a 4 output lvds synthesizer optimized to generate fibre channel reference clock frequencies and is a member of the hiperclocks tm family of high performance clock solutions from idt. using a 26.5625mhz 18pf parallel resonant crystal, the following frequencies can be generated based on the 2 frequency select pins (f_sel[1:0]): 212.5mhz, 187.5mhz, 159.375mhz, 106.25mhz and 53.125mhz. the ics844004-104 uses idt?s 3 rd generation low phase noise vco technology and can achieve <1ps typical rms phase jitter, easily meeting fibre channel jitter requirements. the ics844004-104 is packaged in a 32-pin vfqfn package. features ? four differential lvds outputs ? selectable crystal oscillator interface or lvcmos/lvttl single-ended input ? supports the following output frequencies: 212.5mhz, 187.5mhz, 159.375mhz, 106.25mhz and 53.125mhz ? vco range: 560mhz - 680mhz ? rms phase jitter at 212.5mhz (637khz ? 10mhz), using a 26.5625mhz crystal: <1ps (typical) ? full 3.3v or 2.5v output supply modes ? 0c to 70c ambient operating temperature ? available in both standard (rohs 5) and lead-free (rohs 6) packages table 1. frequency table hiperclocks? ic s inputs output frequency (mhz) input frequency (mhz) f_sel1 f_sel0 m divider value n divider value m/n divider value 26.5625 0 0 24 3 8 212.5 (default) 26.5625 0 1 24 4 6 159.375 26.5625 1 0 24 6 4 106.25 26.5625 1 1 24 12 2 53.125 23.4375 0 0 24 3 8 187.5 (default) 1 1 0 1 0 phase detector vco 637.5mhz (w/26.5625mhz reference) m = 24 (fixed) f_sel[1:0] 0 0 3 0 1 4 1 0 6 1 1 12 2 osc f_sel[1:0] npll_sel nxtal_sel mr ref_clk xtal_in xtal_out q0 nq0 q1 nq1 q2 nq2 q3 nq3 pulldown pulldown pulldown pulldown pulldown 26.5625mhz 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 q0 nq0 mr npll_sel nc nc nc nc q3 nq3 gnd nc nc nxtal_sel ref_clk gnd v dda f_sel0 v dd f_sel1 xtal_out xtal_in nc nc q1 nq1 nc nc nq2 q2 v ddo v ddo block diagram pin assignment ics844004-104 32 lead vfqfn 5mm x 5mm x 0.925mm package body k package top view
ics844004-104 femtoclock?crystal-to-lvds frequency synthesizer idt? / ics? lvds frequency synthesizer 2 ics844004AK-104 rev. a september 15, 2008 table 1. pin descriptions note: pulldown refers to internal input resistors. see table 2, pin characteristics, for typical values. table 2. pin characteristics number name type description 1, 2 q0, nq0 output differential outp ut pair. lvds interface levels. 3 mr input pulldown active high master reset. when logic high, the internal dividers are reset causing the true outputs qx to go low and the inverted outputs nqx to go high. when logic low, the internal dividers and the outputs are enabled. lvcmos/lvttl interface levels. 4 npll_sel input pulldown selects between the pll and ref_clk as input to the dividers. when low, selects pll (pll enable). when high, deselects the reference clock (pll bypass). lvcmos/lvttl interface levels. 5, 6, 7, 8, 15, 16, 20, 21, 28, 29 nc unused no connect. 9v dda power analog supply pin. 10, 12 f_sel0, f_sel1 input pulldown frequency select pin. lvcmos/lvttl interface levels. 11 v dd power core supply pin. 13, 14 xtal_out xtal_in input crystal oscillator interface. xtal_in is the input, xtal_out is the output. 17, 22 gnd power power supply ground. 18 ref_clk input pulldown single-ended reference clock input. lvcmos/lvttl interface levels. 19 nxtal_sel input pulldown selects between crystal or ref_clk inputs as the pll reference source. selects xtal inputs when low. selects ref_clk when high. lvcmos/lvttl interface levels. 23, 24 nq3, q3 output diffe rential output pair. lvds interface levels. 25, 32 v ddo power output supply pins. 26, 27 q2, nq2 output differ ential output pair. lvds interface levels. 30, 31 nq1, q1 output diffe rential output pair. lvds interface levels. symbol parameter test conditio ns minimum typical maximum units c in input capacitance 4 pf r pulldown input pulldown resistor 51 k ?
ics844004-104 femtoclock?crystal-to-lvds frequency synthesizer idt? / ics? lvds frequency synthesizer 3 ics844004AK-104 rev. a september 15, 2008 absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only . functional operation of product at t hese conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc electrical characteristics table 3a. power supply dc characteristics, v dd = v ddo = 3.3v 5%, t a = 0c to 70c table 3b. power supply dc characteristics, v dd = v ddo = 2.5v 5%, t a = 0c to 70c item rating supply voltage, v dd 4.6v inputs, v i -0.5v to v dd + 0.5v outputs, i o continuos current surge current 10ma 15ma package thermal impedance, ja 42.4 c/w (0 mps) storage temperature, t stg -65 c to 150 c symbol parameter test conditions minimum typical maximum units v dd core supply voltage 3.135 3.3 3.465 v v dda analog supply voltage v dd ? 0.12 3.3 v dd v v ddo output supply voltage 3.135 3.3 3.465 v i dd power supply current 105 ma i dda analog supply current 12 ma i ddo output supply current 120 ma symbol parameter test conditio ns minimum typical maximum units v dd core supply voltage 2.375 2.5 2.625 v v dda analog supply voltage v dd ? 0.10 2.5 v dd v v ddo output supply voltage 2.375 2.5 2.625 v i dd power supply current 100 ma i dda analog supply current 10 ma i ddo output supply current 100 ma
ics844004-104 femtoclock?crystal-to-lvds frequency synthesizer idt? / ics? lvds frequency synthesizer 4 ics844004AK-104 rev. a september 15, 2008 table 3c. lvcmos/lvttl dc characteristics, v dd = v ddo = 3.3v 5% or 2.5v 5%, t a = 0c to 70c table 3d. lvds dc characteristics, v dd = v ddo = 3.3v 5%, t a = 0c to 70c table 3e. lvds dc characteristics, v dd = v ddo = 2.5v 5%, t a = 0c to 70c table 4. crystal characteristics note: characterized using an 18pf parallel resonant crystal. symbol parameter test conditio ns minimum typical maximum units v ih input high voltage v dd = 3.3v 2 v dd + 0.3 v v dd = 2.5v 1.7 v dd + 0.3 v v il input low voltage v dd = 3.3v -0.3 0.8 v v dd = 2.5v -0.3 0.7 i ih input high current ref_clk, mr, f_sel[0:1], npll_sel, nxtal_sel v dd = v in = 3.465v or 2.625v 150 a i il input low current ref_clk, mr, f_sel[0:1], npll_sel, nxtal_sel v dd = 3.465v or 2.625v, v in = 0v -5 a symbol parameter test conditio ns minimum typical maximum units v od differential output voltage 300 450 600 mv ? v od v od magnitude change 50 mv v os offset voltage 1.2 1.425 1.65 v ? v os v os magnitude change 50 mv symbol parameter test conditio ns minimum typical maximum units v od differential output voltage 250 400 550 mv ? v od v od magnitude change 50 mv v os offset voltage 1.0 1.2 1.4 v ? v os v os magnitude change 50 mv parameter test conditions mi nimum typical maximum units mode of oscillation fundamental frequency 23.33 26.5625 28.33 mhz equivalent series resistance (esr) 50 ? shunt capacitance 7pf
ics844004-104 femtoclock?crystal-to-lvds frequency synthesizer idt? / ics? lvds frequency synthesizer 5 ics844004AK-104 rev. a september 15, 2008 ac electrical characteristics table 5a. ac characteristics, v dd = v ddo = 3.3v 5%, t a = 0c to 70c note 1: defined as skew between outputs at the same supply vo ltages and with equal load conditions. measured at the differentia l cross points. note 2: this parameter is defined in accordance with jedec standard 65. note 3: please refer to the phase noise plots. table 5b. ac characteristics, v dd = v ddo = 2.5v 5%, t a = 0c to 70c note 1: defined as skew between outputs at the same supply vo ltages and with equal load conditions. measured at the differentia l cross points. note 2: this parameter is defined in accordance with jedec standard 65. note 3: please refer to the phase noise plots. parameter symbol test conditio ns minimum typical maximum units f out output frequency f_sel[1:0] = 00 186.67 226.66 mhz f_sel[1:0] = 01 140 170 mhz f_sel[1:0] = 10 93.33 113.33 mhz f_sel[1:0] = 11 46.67 56.66 mhz t sk(o) output skew; note 1, 2 35 ps t jit(?) rms phase jitter, random; note 3 212.5mhz, (637khz - 10mhz) 0.73 ps 159.375mhz, (637khz - 10mhz) 0.78 ps 106.25mhz, (637khz -10mhz) 0.92 ps 53.125mhz, (637khz - 10mhz) 0.95 ps 187.5mhz, (637khz - 10mhz) 0.75 ps t r / t f output rise/fall time 20% to 80% 250 500 ps odc output duty cycle f_sel[1:0] 3 48 52 % f_sel[1:0] = 3 40 60 % parameter symbol test conditio ns minimum typical maximum units f out output frequency f_sel[1:0] = 00 186.67 226.66 mhz f_sel[1:0] = 01 140 170 mhz f_sel[1:0] = 10 93.33 113.33 mhz f_sel[1:0] = 11 46.67 56.66 mhz t sk(o) output skew; note 1, 2 35 ps t jit(?) rms phase jitter, random; note 3 212.5mhz, (637khz - 10mhz) 0.72 ps 159.375mhz, (637khz - 10mhz) 0.88 ps 106.25mhz, (637khz -10mhz) 0.89 ps 53.125mhz, (637khz - 10mhz) 0.96 ps 187.5mhz, (637khz - 10mhz) 0.74 ps t r / t f output rise/fall time 20% to 80% 250 550 ps odc output duty cycle f_sel[1:0] 3 48 52 % f_sel[1:0] = 3 40 60 %
ics844004-104 femtoclock?crystal-to-lvds frequency synthesizer idt? / ics? lvds frequency synthesizer 6 ics844004AK-104 rev. a september 15, 2008 typical phase noise at 106.25mhz (3.3v) typical phase noise at 212.5mhz (3.3v) fibre channel filter phase noise result by adding a fibre channel filter to raw data raw phase noise data ? ? ? 106.25mhz rms phase jitter (random) 637khz to 10mhz = 0.89ps (typical) noise power dbc hz offset frequency (hz) fibre channel filter phase noise result by adding a fibre channel filter to raw data raw phase noise data ? ? ? 212.5mhz rms phase jitter (random) 637khz to 10mhz = 0.72ps (typical) noise power dbc hz offset frequency (hz)
ics844004-104 femtoclock?crystal-to-lvds frequency synthesizer idt? / ics? lvds frequency synthesizer 7 ics844004AK-104 rev. a september 15, 2008 parameter measureme nt information 3.3v lvds output load ac test circuit output skew output rise/fall time 2.5v lvds output load ac test circuit rms phase jitter output duty cycle/pulse width/period scope qx nqx 3.3v5% power supply +? float gnd lvds v dd, v ddo v dda t sk(o) qx nqx qy nqy v os 20% 80% 80% 20% t r t f v od gnd nq[0:3] qa[0:3} scope qx nqx 2.5v5% power supply +? float gnd lvds v dd, v ddo v dda phase noise mas k offset frequency f 1 f 2 phase noise plot rms jitter = area under the masked phase noise plot noise power nq[0:3] qa[0:3} t pw t period t pw t period odc = x 100%
ics844004-104 femtoclock?crystal-to-lvds frequency synthesizer idt? / ics? lvds frequency synthesizer 8 ics844004AK-104 rev. a september 15, 2008 parameter measurement in formation, continued differential output voltage setup offset voltage setup application information power supply filtering technique as in any high speed analog circuitry, the power supply pins are vulnerable to random noise. to achieve optimum jitter perform- ance, power supply isolation is required. the ics844004-104 provides separate power supplies to isolate any high switching noise from the outputs to the internal pll. v dd, v dda and v ddo should be individually connected to the power supply plane through vias, and 0.01f bypass capacitors should be used for each pin. figure 1 illustrates this for a generic v dd pin and also shows that v dda requires that an additional 10 ? resistor along with a 10 f bypass capacitor be connected to the v dda pin. figure 1. power supply filtering ? ? ? 100 out out lvds dc input v od / ? v od v dd out out lvds dc input ? ? ? v os / ? v os v dd v dd v dda 3.3v or 2.5v 10 ? 10f .01f .01f
ics844004-104 femtoclock?crystal-to-lvds frequency synthesizer idt? / ics? lvds frequency synthesizer 9 ics844004AK-104 rev. a september 15, 2008 crystal input interface the ics844004-104 has been characterized with 18pf parallel resonant crystals. the ca pacitor values shown in figure 2 below were determined using a 26.56 25mhz, 18pf parallel resonant crystal and were chosen to minimize the ppm error. figure 2. crystal input interface lvcmos to xtal interface the xtal_in input can accept a single-ended lvcmos signal through an ac coupling capacitor. a general interface diagram is shown in figure 3. the xtal_out pin can be left floating. the input edge rate can be as slow as 10ns. for lvcmos inputs, it is recommended that the amplitude be re duced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. this configurat ion requires that the output impedance of the driver (ro) plus the series resistance (rs) equals the transmission line impedance. in addition, matched termination at the crystal input will attenuate the signal in half. this can be done in one of two ways. first, r1 and r2 in parallel should equal the transmission line impedance. for most 50 ? applications, r1 and r2 can be 100 ? . this can also be accomplished by removing r1 and making r2 50 ? . figure 3. general diagram for lvcmos driver to xtal input interface xtal_in xtal_out x1 18pf parallel crystal c1 18pf c2 18pf xtal_in xtal_out ro rs zo = ro + rs 50 ? 0.1f r1 r2 v dd v dd
ics844004-104 femtoclock?crystal-to-lvds frequency synthesizer idt? / ics? lvds frequency synthesizer 10 ics844004AK-104 rev. a september 15, 2008 recommendations for unused input and output pins inputs: lvcmos control pins all control pins have internal pulldowns; additional resistance is not required but can be added for additional protection. a 1k ? resistor can be used. ref_clk i nput for applications not requiring th e use of the reference clock, it can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from the ref_clk to ground. outputs: lvds outputs all unused lvds output pairs can be either left floating or terminated with 100 ? across. if they are left floating, we recommend that there is no trace attached. 3.3v, 2.5v lvds driver termination a general lvds interface is shown in figure 4. in a 100 ? differential transmission line environment, lvds drivers require a matched load termination of 100 ? across near the receiver input. for a multiple lvds outputs buffer, if only partial outputs are used, it is recommended to terminate the unused outputs. figure 4. typical lvds driver termination lvds driver r1 100 ? ? + 50 ? 50 ? 3.3v or 2.5v v dd 100 ? differential transmission line
ics844004-104 femtoclock?crystal-to-lvds frequency synthesizer idt? / ics? lvds frequency synthesizer 11 ics844004AK-104 rev. a september 15, 2008 vfqfn epad thermal release path in order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the printed circuit board (pcb) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in figure 5. the solderable area on the pcb, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. sufficient clearance should be designed on the pcb between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. while the land pattern on the pcb provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the pcb to the ground plane(s). the land pattern must be connected to ground through these vias. the vias act as ?heat pipes?. the number of vias (i.e. ?heat pipes?) are application specific and dependent upon the package power dissipation as well as electrical conductivity requirements. thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. it is recommended to use as many vias connected to ground as possible. it is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. this is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal land. precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. note: these recommendations are to be used as a guideline only. for further information, please refer to the application note on the surface mount assembly of am kor?s thermally/electrically enhance leadframe base package, amkor technology. figure 5. p.c. assembly for exposed pad thermal release path ? side view (drawing not to scale) solder solder pin pin exposed heat slug pin pad pin pad ground plane land pattern (ground pad) thermal via
ics844004-104 femtoclock?crystal-to-lvds frequency synthesizer idt? / ics? lvds frequency synthesizer 12 ics844004AK-104 rev. a september 15, 2008 schematic example figure 6 shows an example of ics844004-104 application schematic. in this example, the de vice is operated at vdd = vddo = 3.3v. the 18pf parallel resonant 25mhz crystal is used. the c1 = 33pf and c2 = 22pf are recommended for frequency accuracy. for different board layouts, the c1 and c2 may be slightly adjusted for optimizing frequency accuracy. two examples of lvds for receiver without built-in termination are show in this schematic. figure 6. ics844004-104 schematic example r1 33 nq0 alternate lvds terminat ion c3 0.1uf nq0 r3 50 to logic input pins c4 0.1uf c8 .1uf npll_sel logic control input examples r2 100 set logic input to '1' vdda u1 ics844004-104 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 32 31 30 29 28 27 26 25 q0 nq0 mr npll_sel nc nc nc nc vdda f_sel0 vdd f_sel1 xtal_out xtal_in nc nc gnd ref_clk nxtal_sel nc nc gnd nq3 q3 vddo q1 nq1 nc nc nq2 q2 vddo r1 10 vdd=3.3v rd2 1k ref_clk zo = 50 ohm ru2 not install r4 50 c1 33pf nq3 q3 zo = 50 ohm mr vdd nxtal_sel vdd q3 zo = 50 ohm nq3 rd1 not install zo = 50 ohm x1 25mhz q1 driv er_lvcmos ru1 1k f_sel0 c5 0.01u to logic input pins vddo vdd q0 c2 27pf + - set logic input to '0' vddo + - c7 0.1uf vdd c6 10uf f_sel1 1 8 p f q0 vddo=3.3v zo = 50
ics844004-104 femtoclock?crystal-to-lvds frequency synthesizer idt? / ics? lvds frequency synthesizer 13 ics844004AK-104 rev. a september 15, 2008 power considerations this section provides information on power dissipati on and junction temperature for the ics844004-104. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ics844004-104 is the sum of the core power plus the analog power plus the power dissipated in the load(s). the following is the power dissipation for v dd = 3.3v + 5% = 3.465v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. power (core) max = v dd_max * (i dd_max + i dda_max ) = 3.465v * (105ma + 12ma) = 405.4mw power (outputs) max = v ddo_max * i ddo_max = 3.465v * 120ma = 415.8mw total power_ max = 405.4mw + 415.8mw = 821.2mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. the maximum recommended junction temperature for hiperclocks devices is 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction te mperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming no air flow and a multi-layer board, the appropriate value is 42.4c/w per table 7 below. therefore, tj for an ambient temperature of 70c with all outputs switching is: 70c + 0.821w * 42.4c/w = 104.8c. th is is well below the limit of 125c. this calculation is only an example. tj will obviously vary dependi ng on the number of loaded ou tputs, supply voltage, air flow and the type of board (multi-layer). table 7. thermal resistance ja for 32 lead vfqfn, forced convection ja vs. air flow meters per second 012.5 multi-layer pcb, jedec standard test boards 42.4c/w 37.0c/w 33.2c/w
ics844004-104 femtoclock?crystal-to-lvds frequency synthesizer idt? / ics? lvds frequency synthesizer 14 ics844004AK-104 rev. a september 15, 2008 reliability information table 8. ja vs. air flow table for a 32 lead vfqfn transistor count the transistor count for ics844004-104 is: 2914 package outline and package dimensions package outline - k suffix for vfqfn packages t able 9. package dimensions reference document: jede c publication 95, mo-220 note: the following package mechanical drawing is a generic drawing that applies to any pin count vfqfn package. this drawing is not intended to convey the actual pin count or pin layout of this device. the pin count and pinout are shown on the front page. the package dimensions are in table 8 below. ja vs. air flow meter per second 012.5 multi-layer pcb, jedec standard test boards 42.4c/w 37.0c/w 33.2c/w to p view index area d cham fer 4x 0.6 x 0.6 max optional anvil singula tion a 0. 0 8 c c a3 a1 s eating plan e e2 e2 2 l (n -1)x e (r ef.) (ref.) n & n even n e d2 2 d2 (ref.) n & n odd 1 2 e 2 (ty p.) if n & n are even (n -1)x e (re f.) b th er mal ba se n or jedec variation: vhhd-2/-4 all dimensions in millimeters symbol minimum nominal maximum n 32 a 0.80 1.00 a1 00.05 a3 0.25 ref. b 0.18 0.25 0.30 n d & n e 8 d & e 5.00 basic d2 & e2 3.0 3.3 e 0.50 basic l 0.30 0.40 0.50
ics844004-104 femtoclock?crystal-to-lvds frequency synthesizer idt? / ics? lvds frequency synthesizer 15 ics844004AK-104 rev. a september 15, 2008 ordering information table 10. ordering information note: parts that are ordered with an "lf" suffix to the part number are the pb-free configuration and are rohs compliant. part/order number marking package shipping packaging temperature 844004AK-104 ics4044a104 32 lead vfqfn tray 0 c to 70 c 844004AK-104t ics4044a104 32 lead vfqfn 2500 tape & reel 0 c to 70 c 844004AK-104lf ics004a104l ?lead-free? 32 lead vfqfn tray 0 c to 70 c 844004AK-104lft ics004a104l ?lead-free? 32 lead vfqfn 2500 tape & reel 0 c to 70 c while the information presented herein has been checked for both accuracy and reliability, integrated device technology (idt) a ssumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or licenses are implied. this product is intended for use in normal commercial applications. any other applications, such as those requiring extended temperature ranges, high reliabilit y or other extraordinary environmental requirements are not recommended without additional processing by idt. idt reserv es the right to change any circuitry or specifications with out notice. idt does not authorize or warrant any idt product for use in life support devices or critical medical instruments.
ics844004-104 femtoclock?crystal-to-lv ds frequency synthesizer www.idt.com ? 2008 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt and the idt logo are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other brands, product names a nd marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt.com/go/contactidt technical support netcom@idt.com +480-763-2056 corporate headquarters integrated device technology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800-345-7015 (inside usa) +408-284-8200 (outside usa) contact information: www.idt.com

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